Cita APA

Vaidyanathan, K. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE Digital Library.

Citación estilo Chicago

Vaidyanathan, Kaushik. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE Digital Library.

Cita MLA

Vaidyanathan, Kaushik. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE Digital Library.

Warning: These citations may not always be 100% accurate.